The present invention pertains to integrated circuits, and particularly to MOS circuits using field-effect transistors.
The relatively wide degree of variation in the threshold voltages of FETs has imposed performance limitations on prior art MOS integrated circuits. Threshold voltage is affected by intrinsic factors such as gate oxide thickness and channel impurity concentration, which are caused by inevitable process variations. Threshold voltage is also affected by extrinsic factors such as the ambient temperature in which the device operates. Accordingly, MOS integrated circuits must be designed for the combined worst-case effects of both such intrinsic and extrinsic factors. Furthermore, response time and other device parameters must be specified to reflect the worst-case threshold voltage. These and other problems of the prior art are greatly alleviated by the present invention.